With this circuit, we can actually divide the clock by cascading the previous circuit, as displayed in Fig. As a result, the period of clkdiv (the time between two adjacent rising edges) doubles the period of clk (i.e., the frequency of clkdiv is half of the clk frequency). When the next rising edge of clk occurs, clkdiv will change to logic '1' and din will change back to '0' after the propagation delay of the inverter. As soon as the clkdiv changes to '0', din will be pulled up to logic '1' by the inverter. When the first rising edge of clock arrives, clkdiv is updated by the current din value and changes to '0'. As din inverts the signal clkdiv, din is initially low. There is a simple circuit that can divide the clock frequency by half. The oscillator used on Digilent FPGA boards usually ranges from 50 MHz to 100 MHz however, some peripheral controllers do not need such a high frequency to operate. Usually the clock signal comes from a crystal oscillator on-board. ) always (posedge (clk ), posedge (rst ) ) begin if (rst = 1 )Ī clock signal is needed in order for sequential circuits to function. So the final Verilog implementation of a D-FF looks as follows: In Verilog code:Īlways (posedge (clk ), posedge (rst ) ) begin if (rst = 1 ) So we can describe the circuit as follows: always at rising edge of clk or rising of rst, if rst is asserted, Q is driven to logic '0', else Q is driven by D. In other words, output Q is sensitive to clock signal clk and reset signal rst. On the contrary to combinational circuits, the output of flip-flop changes when a rising edge or falling edge of clock occurs or the reset is asserted. To describe the behavior of the flip-flop, we are going to use an “ always” block. 1 shows, D flip-flops have three inputs: data input (D), clock input ( clk), and asynchronous reset input ( rst, active high), and one output: data output (Q). In this step, we are going to implement a D-FF with asynchronous reset.Īs the block diagram in Fig.